#Build: Synplify Pro H-2013.03M-1 , Build 054R, May 20 2013 #install: C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1 #OS: Windows 7 6.1 #Hostname: CTORGERSEN-PC #Implementation: synthesis $ Start of Compile #Wed Nov 06 18:50:36 2013 Synopsys VHDL Compiler, version comp201303rcp1, Build 114R, built May 21 2013 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @N:CD720 : std.vhd(146) | Setting time resolution to ns @N: : Trigger_receiver_v1_7.vhd(20) | Top entity is set to Trigger_receiver_v1_7. File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core_obfuscated\coreapb3_iaddr_reg.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core_obfuscated\coreapb3_muxptob3.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\Actel\SgCore\OSC\1.0.100\osc_comps.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\ms_event_fifo_ms_event_fifo_0_USRAM_top.vhd changed - recompiling File C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\generic\smartfusion2.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\XHDL_misc.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\XHDL_std_logic.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7\FCCC_0\Trigger_receiver_v1_7_FCCC_0_FCCC.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7_MSS\Trigger_receiver_v1_7_MSS_tmp_syn.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\arbit.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\cnt12.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\cnt20.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\dcs_interface_pkg.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\L1_line_decoder.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\mux_arbit.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\phase_check.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\posdge_pulse.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\rcu_addr_set.vhd changed - recompiling File C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\vhd2008\numeric_bit.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\trigger_receiver_pkg.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\Actel\DirectCore\CoreAPB3\4.0.100\rtl\vhdl\core_obfuscated\coreapb3.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\fifocore_sync.vhd changed - recompiling File C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\vhd2008\misc.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\fifocore_sync_scntr.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\COREFIFO.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7\OSC_0\Trigger_receiver_v1_7_OSC_0_OSC.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7_MSS\Trigger_receiver_v1_7_MSS.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\abs_cnt.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\addressed_msg_decoder.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\addr_decoder.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\apb_to_dcs.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\broadcast_msg_decoder.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\cmd_decoder.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\counters.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\fifo_wrapper.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\hamming_decoder.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\rcu_com_release.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\rcu_reg.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\rcu_dec.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\sequence_validator.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\serialb_com.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\hdl\trigger_receiver.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7\Trigger_receiver_v1_7.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\grayToBinConv.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\ms_event_fifo\ms_event_fifo_0\rtl\vhdl\core_obfuscated\doubleSync.vhd changed - recompiling VHDL syntax check successful! File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7\FCCC_0\Trigger_receiver_v1_7_FCCC_0_FCCC.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7\OSC_0\Trigger_receiver_v1_7_OSC_0_OSC.vhd changed - recompiling File C:\Microsemi\Projects\To_be_handed_to_Taco_01_11-13\component\work\Trigger_receiver_v1_7\Trigger_receiver_v1_7.vhd changed - recompiling @N:CD231 : std1164.vhd(913) | Using onehot encoding for type mvl9plus ('U'="1000000000") @N:CD630 : Trigger_receiver_v1_7.vhd(20) | Synthesizing work.trigger_receiver_v1_7.rtl @N:CD630 : Trigger_receiver_v1_7_MSS.vhd(17) | Synthesizing work.trigger_receiver_v1_7_mss.rtl @N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box Post processing for smartfusion2.inbuf.syn_black_box @N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box Post processing for smartfusion2.tribuff.syn_black_box @N:CD630 : Trigger_receiver_v1_7_MSS_tmp_syn.vhd(10) | Synthesizing work.mss_050.def_arch Post processing for work.mss_050.def_arch Post processing for work.trigger_receiver_v1_7_mss.rtl @N:CD630 : trigger_receiver.vhd(43) | Synthesizing work.trigger_receiver.arc @W:CD326 : trigger_receiver.vhd(306) | Port l2_extendedlatency of entity work.rcu_com_release is unconnected @N:CD630 : counters.vhd(44) | Synthesizing work.counters.arc Post processing for work.counters.arc @N:CD630 : fifo_wrapper.vhd(41) | Synthesizing work.fifo_wrapper.behave @N:CD364 : fifo_wrapper.vhd(163) | Removed redundant assignment @N:CD630 : ms_event_fifo.vhd(19) | Synthesizing work.ms_event_fifo.rtl @N:CD630 : COREFIFO.vhd(13) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_corefifo.cfifol @W:CD638 : COREFIFO.vhd(245) | Signal cfifoo1l is undriven @W:CD638 : COREFIFO.vhd(247) | Signal cfifol1l is undriven @W:CD638 : COREFIFO.vhd(253) | Signal cfifol0l is undriven @W:CD638 : COREFIFO.vhd(259) | Signal cfifoi0l is undriven @W:CD638 : COREFIFO.vhd(285) | Signal cfifoi0i is undriven @N:CD630 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(10) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper.generated @N:CD630 : ms_event_fifo_ms_event_fifo_0_USRAM_top.vhd(8) | Synthesizing corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_usram_top.def_arch @N:CD630 : smartfusion2.vhd(620) | Synthesizing smartfusion2.ram64x18.syn_black_box Post processing for smartfusion2.ram64x18.syn_black_box @N:CD630 : smartfusion2.vhd(575) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box @N:CD630 : smartfusion2.vhd(569) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(342) | Synthesizing smartfusion2.inv.syn_black_box Post processing for smartfusion2.inv.syn_black_box Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_usram_top.def_arch Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_ram_wrapper.generated @N:CD630 : fifocore_sync_scntr.vhd(13) | Synthesizing corefifo_obf_lib.cfifolil.cfifol @W:CD638 : fifocore_sync_scntr.vhd(108) | Signal cfifooiil is undriven Post processing for corefifo_obf_lib.cfifolil.cfifol @W:CL169 : fifocore_sync_scntr.vhd(245) | Pruning register CFIFOL0il @W:CL169 : fifocore_sync_scntr.vhd(237) | Pruning register CFIFOl1OL @W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOoOLl assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(279) | All reachable assignments to CFIFOLOll assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOi1OL assign '0'; register removed by optimization @W:CL111 : fifocore_sync_scntr.vhd(253) | All reachable assignments to CFIFOO1oL assign '0'; register removed by optimization Post processing for corefifo_obf_lib.ms_event_fifo_ms_event_fifo_0_corefifo.cfifol Post processing for work.ms_event_fifo.rtl Post processing for work.fifo_wrapper.behave @N:CD630 : phase_check.vhd(37) | Synthesizing work.phase_check.behave Post processing for work.phase_check.behave @N:CD630 : sequence_validator.vhd(40) | Synthesizing work.sequence_validator.behave @N:CD231 : sequence_validator.vhd(93) | Using onehot encoding for type state (s_idle="100000000") @W:CD604 : sequence_validator.vhd(253) | OTHERS clause is not synthesized @W:CD434 : sequence_validator.vhd(189) | Signal timeout_counter in the sensitivity list is not used in the process Post processing for work.sequence_validator.behave @W:CL169 : sequence_validator.vhd(261) | Pruning register timeout_counter(3 downto 0) @W:CL169 : sequence_validator.vhd(261) | Pruning register pre_pulseR @W:CL190 : sequence_validator.vhd(261) | Optimizing register bit prepulse_error to a constant 0 @W:CL169 : sequence_validator.vhd(261) | Pruning register prepulse_error @N:CD630 : L1_line_decoder.vhd(37) | Synthesizing work.l1_line_decoder.behave Post processing for work.l1_line_decoder.behave @N:CD630 : addressed_msg_decoder.vhd(41) | Synthesizing work.addressed_message_decoder.arc @N:CD231 : addressed_msg_decoder.vhd(68) | Using onehot encoding for type state (s_idle="10000000000000") Post processing for work.addressed_message_decoder.arc @N:CD630 : broadcast_msg_decoder.vhd(41) | Synthesizing work.broadcast_message_decoder.behave Post processing for work.broadcast_message_decoder.behave @N:CD630 : hamming_decoder.vhd(39) | Synthesizing work.hamming_decoder.behave Post processing for work.hamming_decoder.behave @N:CD630 : serialb_com.vhd(39) | Synthesizing work.serialb_com.behave @N:CD231 : serialb_com.vhd(55) | Using onehot encoding for type state (s_idle="1000000") @W:CD604 : serialb_com.vhd(148) | OTHERS clause is not synthesized Post processing for work.serialb_com.behave @N:CD630 : rcu_com_release.vhd(41) | Synthesizing work.rcu_com_release.arc Post processing for work.rcu_com_release.arc Post processing for work.trigger_receiver.arc @N:CD630 : smartfusion2.vhd(779) | Synthesizing smartfusion2.sysreset.syn_black_box Post processing for smartfusion2.sysreset.syn_black_box @N:CD630 : rcu_dec.vhd(64) | Synthesizing work.rcu_dec.a_rcudec @W:CD638 : rcu_dec.vhd(449) | Signal d_siu_rst is undriven @N:CD630 : abs_cnt.vhd(27) | Synthesizing work.abs_cnt.a_abscnt @N:CD630 : cnt12.vhd(19) | Synthesizing work.cnt12.a_cnt12 Post processing for work.cnt12.a_cnt12 @N:CD630 : posdge_pulse.vhd(20) | Synthesizing work.posedge_pulse.a_posedge_pulse Post processing for work.posedge_pulse.a_posedge_pulse @N:CD630 : cnt20.vhd(19) | Synthesizing work.cnt20.a_cnt20 Post processing for work.cnt20.a_cnt20 Post processing for work.abs_cnt.a_abscnt @N:CD630 : rcu_reg.vhd(62) | Synthesizing work.rcu_reg.a_rcureg @W:CD434 : rcu_reg.vhd(203) | Signal clk in the sensitivity list is not used in the process @W:CD434 : rcu_reg.vhd(265) | Signal rst in the sensitivity list is not used in the process Post processing for work.rcu_reg.a_rcureg @W:CL117 : rcu_reg.vhd(205) | Latch generated from process for signal st_meb_full; possible missing assignment in an if or case statement. @N:CD630 : cmd_decoder.vhd(21) | Synthesizing work.cmd_decoder.a_cmddecoder Post processing for work.cmd_decoder.a_cmddecoder @N:CD630 : addr_decoder.vhd(23) | Synthesizing work.addr_decoder.a_addrdecoder Post processing for work.addr_decoder.a_addrdecoder @N:CD630 : arbit.vhd(15) | Synthesizing work.arbit.a_arbit @N:CD233 : arbit.vhd(36) | Using sequential encoding for type sm @W:CD604 : arbit.vhd(110) | OTHERS clause is not synthesized @W:CD604 : arbit.vhd(139) | OTHERS clause is not synthesized Post processing for work.arbit.a_arbit @N:CD630 : mux_arbit.vhd(20) | Synthesizing work.mux_arbit.a_muxarbit Post processing for work.mux_arbit.a_muxarbit @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal siu_dout(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_data(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal dcs_dout(31 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_add(15 downto 0); possible missing assignment in an if or case statement. @W:CL117 : mux_arbit.vhd(50) | Latch generated from process for signal rcu_we; possible missing assignment in an if or case statement. Post processing for work.rcu_dec.a_rcudec @N:CD630 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_osc_0_osc.def_arch @N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch Post processing for work.rcosc_25_50mhz.def_arch Post processing for work.trigger_receiver_v1_7_osc_0_osc.def_arch @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(12) | RCOSC_25_50MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @N:CD630 : Trigger_receiver_v1_7_FCCC_0_FCCC.vhd(8) | Synthesizing work.trigger_receiver_v1_7_fccc_0_fccc.def_arch @N:CD630 : smartfusion2.vhd(787) | Synthesizing smartfusion2.ccc.syn_black_box Post processing for smartfusion2.ccc.syn_black_box @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box Post processing for smartfusion2.clkint.syn_black_box Post processing for work.trigger_receiver_v1_7_fccc_0_fccc.def_arch @N:CD630 : coreapb3.vhd(14) | Synthesizing coreapb3_lib.coreapb3.capb3ioi @W:CD604 : coreapb3.vhd(440) | OTHERS clause is not synthesized @W:CD638 : coreapb3.vhd(364) | Signal capb3olil is undriven @N:CD630 : coreapb3_muxptob3.vhd(14) | Synthesizing coreapb3_lib.capb3il.capb3o0 Post processing for coreapb3_lib.capb3il.capb3o0 Post processing for coreapb3_lib.coreapb3.capb3ioi @N:CD630 : apb_to_dcs.vhd(9) | Synthesizing work.apb_to_dcs.arc @N:CD233 : apb_to_dcs.vhd(53) | Using sequential encoding for type state @W:CD604 : apb_to_dcs.vhd(131) | OTHERS clause is not synthesized Post processing for work.apb_to_dcs.arc Post processing for work.trigger_receiver_v1_7.rtl @N:CL201 : apb_to_dcs.vhd(96) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL246 : apb_to_dcs.vhd(21) | Input port bits 31 to 20 of paddr(31 downto 0) are unused @W:CL159 : coreapb3.vhd(50) | Input iaddR is unused @W:CL159 : coreapb3.vhd(51) | Input PRESetn is unused @W:CL159 : coreapb3.vhd(52) | Input PCLK is unused @W:CL159 : coreapb3.vhd(82) | Input prdataS0 is unused @W:CL159 : coreapb3.vhd(83) | Input PRdatas1 is unused @W:CL159 : coreapb3.vhd(84) | Input Prdatas2 is unused @W:CL159 : coreapb3.vhd(85) | Input prdatAS3 is unused @W:CL159 : coreapb3.vhd(86) | Input PRDATAS4 is unused @W:CL159 : coreapb3.vhd(88) | Input prdataS6 is unused @W:CL159 : coreapb3.vhd(89) | Input PRDATAs7 is unused @W:CL159 : coreapb3.vhd(91) | Input PRDATas9 is unused @W:CL159 : coreapb3.vhd(92) | Input PRDATAs10 is unused @W:CL159 : coreapb3.vhd(93) | Input PRdatas11 is unused @W:CL159 : coreapb3.vhd(94) | Input PRDATas12 is unused @W:CL159 : coreapb3.vhd(95) | Input PRDatas13 is unused @W:CL159 : coreapb3.vhd(96) | Input PRDATAS14 is unused @W:CL159 : coreapb3.vhd(97) | Input PRDATAS15 is unused @W:CL159 : coreapb3.vhd(99) | Input PREadys0 is unused @W:CL159 : coreapb3.vhd(100) | Input preadys1 is unused @W:CL159 : coreapb3.vhd(101) | Input preadys2 is unused @W:CL159 : coreapb3.vhd(102) | Input preadys3 is unused @W:CL159 : coreapb3.vhd(103) | Input PREADYS4 is unused @W:CL159 : coreapb3.vhd(105) | Input preadys6 is unused @W:CL159 : coreapb3.vhd(106) | Input preadys7 is unused @W:CL159 : coreapb3.vhd(108) | Input PReadys9 is unused @W:CL159 : coreapb3.vhd(109) | Input preadys10 is unused @W:CL159 : coreapb3.vhd(110) | Input PREADYS11 is unused @W:CL159 : coreapb3.vhd(111) | Input pREADYS12 is unused @W:CL159 : coreapb3.vhd(112) | Input preadyS13 is unused @W:CL159 : coreapb3.vhd(113) | Input PREAdys14 is unused @W:CL159 : coreapb3.vhd(114) | Input Preadys15 is unused @W:CL159 : coreapb3.vhd(116) | Input PSLVerrs0 is unused @W:CL159 : coreapb3.vhd(117) | Input pslverrs1 is unused @W:CL159 : coreapb3.vhd(118) | Input PSlverrs2 is unused @W:CL159 : coreapb3.vhd(119) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.vhd(120) | Input pslverRS4 is unused @W:CL159 : coreapb3.vhd(122) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.vhd(123) | Input Pslverrs7 is unused @W:CL159 : coreapb3.vhd(125) | Input pslVERRS9 is unused @W:CL159 : coreapb3.vhd(126) | Input PSLVERrs10 is unused @W:CL159 : coreapb3.vhd(127) | Input PSLverrs11 is unused @W:CL159 : coreapb3.vhd(128) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.vhd(129) | Input pslverrs13 is unused @W:CL159 : coreapb3.vhd(130) | Input Pslverrs14 is unused @W:CL159 : coreapb3.vhd(131) | Input pslverRS15 is unused @W:CL159 : Trigger_receiver_v1_7_OSC_0_OSC.vhd(10) | Input XTL is unused @N:CL201 : arbit.vhd(44) | Trying to extract state machine for register pr_st Extracted state machine for register pr_st State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : rcu_dec.vhd(197) | Input fsmrd_st_a is unused @W:CL159 : rcu_dec.vhd(198) | Input fsmwr_st_b is unused @N:CL201 : serialb_com.vhd(72) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 7 reachable states with original encodings of: 0000001 0000010 0000100 0001000 0010000 0100000 1000000 @W:CL246 : broadcast_msg_decoder.vhd(45) | Input port bits 7 to 3 of brcdata(7 downto 0) are unused @N:CL201 : sequence_validator.vhd(172) | Trying to extract state machine for register current_state Extracted state machine for register current_state State machine has 9 reachable states with original encodings of: 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 @W:CL159 : sequence_validator.vhd(46) | Input pre_pulse is unused @W:CL159 : sequence_validator.vhd(71) | Input L1_msg_tw_passed is unused @W:CL159 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(27) | Input RCLOCK is unused @W:CL159 : ms_event_fifo_ms_event_fifo_0_ram_wrapper.vhd(28) | Input WCLOCK is unused @W:CL159 : COREFIFO.vhd(62) | Input MEmrD is unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 116MB peak: 141MB) Process took 0h:00m:06s realtime, 0h:00m:06s cputime # Wed Nov 06 18:50:42 2013 ###########################################################]